1. Field of the Invention
This invention relates to a timing signal generating circuit in an electronic device which requires a plurality of repeated timing signals for its operation.
2. Description of the Prior Art
In an electronic device such as a magnetic bubble memory and a core memory, a large number of timing signals are required during one basic operation cycle. In order to generate these timing signals, a timing signal generating circuit is provided.
As a prior-art timing signal generating circuit of this type, there has been known a circuit arrangement wherein a plurality of clock signals derived from a clock source are respectively applied to circuits each including monostable multivibrators connected in two stages and wherein outputs from the circuits are used as the timing signals. With such a circuit arrangement, however, a large number of monostable multivibrators are necessary, so that the number of constituent parts is large, resulting in a large size, a high cost and a low reliability. Another problem is that, on account of the dispersions or deviations of the components, the times or positions and the durations or widths of the timing signals deviate.
A circuit arrangement as disclosed in, for example, Japanese Patent Application, Laying-Open No. 1423/76 has therefore been proposed, according to which clock signals from a clock source are counted by a counter, outputs of the counter are applied as address inputs of a read only memory (hereinbelow, abbreviated to "ROM"), and outputs of the ROM are set in a latch circuit with the clock signals, thereby to form the timing signals. With such a circuit arrangement, however, the capacity of the ROM is large, so that the number of circuit constituent elements is large. In point of packaging, the chip size becomes large, and the fabrication of the circuit arrangement in the form of an integrated circuit is difficult. Another problem is the delay time attributed to the ROM.